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The impact of MOS transistors mismatching becomes very important because the dimensions of the devices are reduced and the available signal swings decrease.

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To obtain a better circuit design, the physical origin of this effect has been discussed in several studies Pelgrom et al. Thanks to the use of a fully-balanced pseudo-differential topology, with this inherent positive feedback compensation providing the system with an enhancement of the differential dc-gain, distortion resulting from mismatch is small. As mentioned above, the existing negative resistance enables small variations in dimensions of M N transistors and bias current sources I BIAS to be controlled.

In order to obtain a good matching, the minimum channel length related to the considered CMOS technology must be avoided. However, high frequency operation requires short channels, relying on the negative resistance to obtain the adequate matching between transistors in the signal path. In addition, channel length modulation is not considered, as it only has a substantial effect on integrator response linearity at low frequencies, where distortion is suppressed by feedback Smith et al.


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In consequence, transistors are assumed to be well matched, which will be achieved by means of a lower mismatching sensitive design while obtaining the final layout. Mismatching between transistors also degrades the outstanding benefits provided by balanced structures, since they depend strongly on the symmetry of the circuit. Therefore, mismatching can also be reflected in unbalanced signal paths.

Post-layout simulations have been accomplished regarding sensitivity to this unbalance for both HS and FC transconductor implementations. As a result, we can conclude that the proposed topology is quite insensitive to transistor mismatching.

In addition to this, the effect of common-mode signal mismatching is alleviated by means of feedback compensation, as previously explained, thus supporting the proposed design strategy. Apart from the usual requirements associated with high frequency CMOS filter design, the issue of programmability brings to the forefront the considerable problem of maintaining performances such as frequency response accuracy, noise and dynamic range across the entire tuning range. Requirements of robust and precise implementation of filtering systems in the VHF range point to programmable G m -C continuous-time filters as the best option for obtaining a wide programming range usually The fact of considering both effects at the same time means that the unity-gain frequency t of each integrator in the filter should be electronically variable over a wide range.

Lower supply voltages required by current digital CMOS technologies make the use of conventional continuous tuning techniques over a wide frequency range very difficult due to their effect on dynamic range and non-linear distortion. These techniques are based on the variation of the transistors biasing points, limiting their application to compensate the inherent changes due to temperature and the technological process. Therefore, discrete tuning is the best option to preserve the dynamic range DR.

There are three different ways of achieving this wide range of variability: the capacitor, the transconductor or both can be made programmable. At high frequencies, the integrating capacitances are relatively small. If they are replaced by capacitor arrays to obtain C-programmability, the net parasitic capacitances at the terminals of the array can be quite large when the array is implementing the lowest effective capacitance, which is a very difficult problem to solve.

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In addition to this, switchable array of capacitors provides high precision on filters though the existence of switches in the signal path. So, the constant-C scaling technique is the option considered, leading to the desired programmability by varying G m discretely while maintaining the noise specifications over the entire frequency range.

Furthermore, lower power consumption is achieved at low frequency values of the programming range. This is the best option for maintaining a trade-off between noise specifications, power consumption and programming range Pavan et al. Two different strategies can be used to extend the tuning range and preserve DR: switchable array of degenerating MOS resistors and parallel connection of identical transconductors switched by a digital word.

The first one uses the same transconductor and capacitor throughout the whole frequency range whilst the degeneration resistor R is formed by a parallel connection of MOS triode transistors Bollati et al. This technique involves variations over the entire frequency range of the noise factor, which is proportional to the degenerated resistor, generating dynamic range variations.

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Phase errors will also appear, achieving the worst situation for both undesirable parameters in the opposite ends of the frequency range: minimum DR maximum R for the lowest frequency f min , and maximum phase error for the highest frequency f max. However, this strategy leads to the simplest structure, with a small active area and lower power consumption.

The second strategy consists of a parallel connection of identical transconductors obtaining a programmable array where the desired time-constant can be digitally tuned Pavan et al. This solution is the best option for VHF applications. However, its main drawbacks are power consumption and area, proportional to the number of connected active cells. Considering all these ideas, the latter strategy is the technique selected for achieving the desired programmability for the proposed topology.

Programmability using a parallel connection of conventional differential pairs has been published previously Pavan et al. Therefore, the total tunable range will be greater than the nominal one. Our proposal is to achieve a digitally programmable transconductor, specifically designed for a wide programmability range comprised of parallel connection of unit cells. Figure 11 shows the conceptual scheme of a 3-bit programmable cell.

This topology presents two main drawbacks; the need for additional transistors in the signal path and the variation of parasitic capacitances C pin and C pout depending on the digital word. However, it is necessary to keep the dynamic range constant for each g m value and the total node parasitic capacitances over the entire programming range. This solution is adopted for the proposed transconductor topology, giving a HS implementation with a programmable range from Figure 12 a and a FC implementation with a varying range from Figure 12 b. Each cascode unit cell Figure 6 , i.

The connecting lines of the substrate terminals are not shown on these schematics as the explanation has already been given in previous sections. The other disadvantage inherent to this topology can be also alleviated with an additional design strategy. When a change in the digital word occurs, some transistors change from saturation to cut-off region and vice versa , and different contributions to total input node.

This change can generate a shift in the desired frequency and Q-factor variations, limiting the integrator and filter performance. In consequence, the implementation of each unit cell has been modified by using dummy elements connected at the input, which allow us to make the input capacitance independent of the digital word, maintaining the same parasitic capacitances on the signal processing nodes Pavan et al. Note that the total output parasitic capacitance —junction extrinsic capacitance— is also constant because it has almost the same value for cut-off or saturation transistors Tsividis, , Tsividis, As the output conductance is proportional to the transconductance, the differential dc-gain is maintained irrespective of the digital word.

Consequently, the relative shape of the frequency response, output noise power and dynamic range are independent of the digital word. Therefore, we obtain the desired programmable transconductor with no switches in the signal path by driving the gates of bias and cascode transistors with a digital word modulated with the adequate analog value. The power consumption is proportional to the necessary transconductance in each frequency range.

Two different integrators have been implemented. The first one is based on the HS topology, considering the total input node parasitic capacitance —basically gate-source capacitances— as the total integration capacitance with no need for any external capacitors, in order to reach the maximum operation frequency with moderate power consumption. Therefore, for this situation, maintaining the integration capacitance constant becomes essential and its value can be controlled by means of the dummy-based system.

Figure 13 a plots the post-layout simulation results for HS implementation and shows the variation of unity-gain frequency versus digital word value. The expected linear dependence of the transconductance and the constant integration capacitance are observed, and a programming range from 28 to MHz is obtained by varying the digital word. However, a marked phase lag due to parasitic effects parasitic zero s 0 at high frequency was detected, as expected. A possible compensation scheme, is based on two capacitors, C C , implemented with dummy MOS transistors and connected in a cross-coupled manner as shown in Figure 7 a.

Unity-gain frequency and phase vs. Total integration capacitance is once more maintained constant by means of the dummy-based system and Figure 13 b plots the post-layout simulation results. The first curve plots the variation of the transconductance as a function of the digital word when no external capacitance is connected at the input; a non-linear response is obtained, due to the expected parasitic poles and zeros.

When connecting the external capacitance, the expected linear dependence is obtained, providing the system with coarse tuning.

Nevertheless, a phase shift is obtained even when the compensation scheme based on the two cross-coupled capacitors C C is used. Next step involves a resistance R being connected at the input in series with the external capacitance, as shown in Figure 7 b. This resistor is implemented with a transistor working in the linear region and is the best option to compensate this phase error.

Therefore, by varying the digital word, the unity-gain frequency is controlled and the phase error is effectively reduced over the entire programming range. Then, to control the operation frequency and to reduce the phase error, a shunt connection is made at the input between a resistance and the integration capacitance C I. We can define the transconductor input voltage variations around the bias point V C as shown in Figure 3.

The linear input range is constant for digital scaling of the transconductance as shown in Figure The variation of the g m as a function of the digital word is presented, providing the system with coarse tuning. Therefore, by means of a parallel connection of equal transconductors switched by a digital word we guarantee that the DR for each g m value and the total external node capacitances will be kept constant. Transconductance as a function of the digital word coarse tuning for the: a HS implementation; b FC implementation.

On the other hand, fine tuning can be achieved if necessary, as the transconductance value can be controlled by varying the bias current source for a fixed digital word. Hence, discrete steps are swept by varying the bias current while maintaining the same dynamic range. Therefore, a complete control of the frequency response can be obtained. The trade-off between transconductance and linear input range is shown in Figure 15 for both topologies.

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Transconductance versus biasisng currents fine tuning for the: a HS implementation; b FC implementation. To conclude, the proposed structure is a balanced topology aimed at improving immunity to digital noise and linearity. A digitally programmable transconductor has been designed, maintaining the same dynamic range over the entire frequency range.

Therefore, it can be used in the design of programmable filters, as the expected characteristics of a programmable cell will be obtained: to maintain Q-factor, noise power and maximum signal swing constant over the entire programming range, leading to a DR independent on the operation frequency.

The expected linear dependence of the unity-gain frequency is obtained and the phase error is effectively reduced over the entire programming range in both implementations, with a compensation scheme based on two cross-coupled capacitors for the HS topology and the classical RC circuit connected at the input for the FC approach. To demonstrate the theoretical advantages of this approach for a programmable transconductor suitable for VHF, two 3-bit programmable integrators have been designed.

The dimensions of the transistors were chosen in order to cover all the design requirements obtained in this chapter, leading to a complete sweep of the discrete step by varying the bias current. In this way, for the HS implementation, the operation point is located at 90 A and the bias current adjustment is possible from A. However, for the FC implementation, the operating point is located at A, covering the digital step by varying the bias current from A.

In this way, the discrete tunability requirement is obtained but the FC transconductance value at the operation point is maximised. A careful layout has been drawn out to obtain all the characteristics associated with the proposed design accurately and demonstrate the feasibility of the intended approach. As stated below, we have taken special care to get rid of the unwanted effects related to parasitic elements and mismatching Baker et al. All the designs have been carried out taking into account the specific design rules for high frequency operation, which are highly appropriate for obtaining good matching between components.

Interdigitized and common-centroid layout techniques have been considered to reduce the variations of threshold voltage, which are associated with gradients in gate-oxide thickness. Guard rings have been included in the design with the aim of reducing substrate noise. Bond-pads have also been carefully laid out and, in this way, input and output pins have been placed as far as possible between them. Balanced structures provide outstanding benefits, but they are strongly dependent on the symmetry of the circuit.

Consequently, special care has been taken to outline the paths of the balanced signals, in an attempt to ensure the best matching between them. MOS devices have fragile gates seeing that electrostatic discharges may cause destruction of the device if the oxide breakdown voltage is exceeded. Considering this point, we concluded that it would be advisable to provide the transistors that control the quality factor of the circuit with a path protection system. The scheme chosen to achieve this goal was the anti-parallel diodes configuration. This circuit is very straightforward and simple but is sufficient for the purposes of this work.

Figure 16 a shows the drawn layout of the HS test chip with an active area of 0. Figure 16 b shows the microphotograph of the programmable FC transconductor, with an active area of 0. The area of the FC active element is 0.